1. Field
This application relates generally to semiconductor devices and to methods of making the devices.
2. Background of the Technology
In junction field-effect devices used in power switching applications, it is often highly desirable to not only reduce the channel resistance but also provide a MOSFET-like switching behavior. In particular, once the channel is pinched-off by the threshold voltage applied to the gate, it would be desirable if the device can block the maximum or rated voltage. Such device property requires infinitely high voltage blocking gain β. In junction field-effect devices, low channel resistance and high voltage blocking gain are typically viewed as competing device characteristics. For example, in short-channel JFETs or SITs, the channel component of the total device resistance is relatively small and current saturation is much less pronounced than in longer channel JFET structures. However, the voltage-blocking gain is also small and the difference between the threshold voltage and the gate bias required to block the maximum drain voltage is very significant, reaching in some cases tens of volts (e.g., Merrett et al. [1]). On the other hand, in long channel enhancement-mode JFETs that can provide high voltage-blocking gain, the current saturates too early to fully utilize relatively low on-state channel resistance in the linear region (e.g., Zhao et al. [2] and Sannuti et al. [3]). This problem is especially pronounced in the case of power SiC VJFETs. As a result, the development of normally-off switching devices has been impaired.
Accordingly, there still exists a need for junction field-effect semiconductor devices having low on-state channel resistance and high voltage-blocking gain.